This article provides information about the communications aspects of Universal Serial Bus (USB): Signaling, Protocols, Transactions.
USB is an industry-standard used to specify cables, connectors, and protocols that are used for communication between electronic devices. USB ports and cables are used to connect hardware such as printers, scanners, keyboards, mice, flash drives, external hard drives, joysticks, cameras, monitors, and more to computers of all kinds. USB also supports signaling rates from 1.5 Mbit/s (Low speed) to USB 80Gbps (USB4 Gen 4) depending on the version of the standard. The article explains how USB devices transmit and receive data using electrical signals over the physical layer, how they identify themselves and negotiate parameters such as speed and power with the host or other devices using standard protocols such as USB Device Framework and USB Power Delivery, and how they exchange data using packets of different types and formats such as token, data, handshake, and special packets.
Signaling (USB PHY) Signaling rate (transmission rate) + Comparison of signaling rates Logo Label Operation mode Signaling rate Typical data rates Introduced in Basic-Speed Low-Speed 1.5 Mbit/s (187.5 KB/s) USB 1.0 Full-Speed 12 Mbit/s (1.5 MB/s) USB 1.0 High-Speed High-Speed 480 Mbit/s (60 MB/s) R: 30–42 MB/sW: 25–30 MB/s USB 2.0 USB 5Gbps USB 3.2 Gen 1×1 5 Gbit/s (625 MB/s) R: 90–110 MB/sW: 70–90 MB/s USB 3.0 USB 10Gbps USB 3.2 Gen 2×1 10 Gbit/s (1.25 GB/s) USB 3.1 USB 20Gbps USB 3.2 Gen 2×2 20 Gbit/s (2.5 GB/s) USB 3.2 USB 40Gbps USB4 Gen 3×2 40 Gbit/s (5 GB/s) USB4 USB 80Gbps USB4 Gen 4×2 80 Gbit/s (10 GB/s) USB4 Version 2.0
The maximum signaling rate in USB 2.0 is 480 Mbit/s (60 MB/s) per controller and is shared amongst all attached devices. Some personal computer chipset manufacturers overcome this bottleneck by providing multiple USB 2.0 controllers within the southbridge.
In practice and including USB protocol overhead, data rates of 320 Mbit/s (38 MB/s) are sustainable over a high-speed bulk endpoint. Throughput can be affected by additional bottlenecks, such as a hard disk drive as seen in routine testing performed by CNet, where write operations to typical high-speed hard drives sustain rates of 25–30 MB/s, and read operations at 30–42 MB/s; this is 70% of the total available bus bandwidth. For USB 3.0, typical write speed is 70–90 MB/s, while read speed is 90–110 MB/s. Mask tests, also known as eye diagram tests, are used to determine the quality of a signal in the time domain. They are defined in the referenced document as part of the electrical test description for the high speed (HS) mode at 480 Mbit/s.
According to a USB-IF chairman, "at least 10 to 15 percent of the stated peak 60 MB/s (480 Mbit/s) of Hi-speed USB goes to overhead—the communication protocol between the card and the peripheral. Overhead is a component of all connectivity standards". Tables illustrating the transfer limits are shown in Chapter 5 of the USB spec.
For isochronous devices like audio streams, the bandwidth is constant and reserved exclusively for a given device. The bus bandwidth therefore only has an effect on the number of channels that can be sent at a time, not the speed or latency of the transmission.
Low speed (LS) rate of 1.5 Mbit/s is defined by USB 1.0. It is very similar to full-bandwidth operation except each bit takes 8 times as long to transmit. It is intended primarily to save cost in low-bandwidth human interface devices (HID) such as keyboards, mice, and joysticks. Full speed (FS) rate of 12 Mbit/s is the basic USB signaling rate defined by USB 1.0. All USB hubs can operate at this rate. High speed (HS) rate of 480 Mbit/s was introduced in 2001 by USB 2.0. High-speed devices must also be capable of falling back to full-speed as well, making high-speed devices backward compatible with USB 1.1 hosts. Connectors are identical for USB 2.0 and USB 1.x. SuperSpeed (SS) rate of 5.0 Gbit/s. The written USB 3.0 specification was released by Intel and its partners in August 2008. The first USB 3.0 controller chips were sampled by NEC in May 2009, and the first products using the USB 3.0 specification arrived in January 2010. USB 3.0 connectors are generally backward compatible, but include new wiring and full-duplex operation. SuperSpeed+ (SS+) rate of 10 Gbit/s is defined by USB 3.1, and 20 Gbit/s using two lanes is defined by USB 3.2.
Framing The host controller divides bus time into 1 ms frames when using low speed (1.5 Mbit/s) and full speed (12 Mbit/s), or 125 μs microframes when using high speed (480 Mbit/s), during which several transactions may take place.
Electrical specification USB signals are transmitted using differential signaling on a twisted-pair data cable with characteristic impedance.
Low speed (LS) and Full speed (FS) modes use a single data pair, labelled D+ and D−, in half-duplex. Transmitted signal levels are for logical low, and for logical high level. The signal lines are not terminated. High speed (HS) mode uses the same wire pair, but with different electrical conventions. Lower signal voltages of for low and for logical high level, and termination of 45 Ω to ground or 90 Ω differential to match the data cable impedance. SuperSpeed (SS) adds two additional pairs of shielded twisted wire (and new, mostly compatible expanded connectors). These are dedicated to full-duplex SuperSpeed operation. The half-duplex lines are still used for configuration. Logic levels are defined not in terms of voltage levels but in terms of voltage transitions. The voltage varies between ±500 mV (±20%) during a transition in normal mode and between ±200 - 600 mV (depending on the transmitter) in low power mode. SuperSpeed+ (SS+) uses increased signaling rate (Gen 2×1 mode) and/or the additional lane in the Type-C connector (Gen 1×2 and Gen 2×2 mode).
A USB connection is always between a host or hub at the A connector end, and a device or hub's upstream port at the other end.
Signaling state The host includes 15 kΩ pull-down resistors on each data line. When no device is connected, this pulls both data lines low into the so-called single-ended zero state (SE0 in the USB documentation), and indicates a reset or disconnection.
Line transition state The following terminology is used to assist in the technical discussion regarding USB PHY signaling.
Signal Line transition state Description Low speed(D− pull-up) Full speed(D+ pull-up) D+ D− D+ D− J Same as idle line state This is present during a transmission line transition. Alternatively, it is waiting for a new packet. low high high low K Inverse of J state This is present during a transmission line transition. high low low high SE0 Single-ended zero Both D+ and D− are low. This may indicate an end of packet signal or a detached USB device. low low low low SE1 Single-ended one This is an illegal state and should never occur. This is seen as an error. high high high high
The idle line state is when the device is connected to the host with a pull-up on either D+ (for full speed USB 1.x) or D− (for low speed USB 1.x), with transmitter output on both host and device is set to high impedance (hi-Z) (disconnected output). A USB device pulls one of the data lines high with a 1.5 kΩ resistor. This overpowers one of the 15 kΩ pull-down resistors in the host and leaves the data lines in an idle state called J. For USB 1.x, the choice of data line indicates what signal rates the device is capable of: full-bandwidth devices pull D+ high, low-bandwidth devices pull D− high. The K state has opposite polarity to the J state.
Line state (covering USB 1.x and 2.x) Line state/signal Description Low speed Full speed High speed Detached No device detected. Both lines are pulled down by 15 kΩ pull-down resistors on the host side. SE0 ≥ 2 μs Connect USB device pulls up either D+ or D− to wake the host from the detached line state. This starts the USB enumeration process. This sets the idle state. D− pull-up D+ pull-up As full speed, then chirp in reset Idle / J Host and device transmitter at Hi-Z. Sensing line state in case of detached state. As detached or connect state. Sync Start of a packet line transition pattern. KJKJKJKK 15 × KJ, then KK, for 32 symbols total. EOP End of packet line transition pattern. SE0, SE0, J Reset Reset USB device to a known initial state. SE0 ≥ 2.5 ms Suspend Power down the device, such that it would only consume 2.5 mA from VBUS. Exits this state only after a resume or reset signal is received. To avoid this state a SOF packet (high speed) or a keep alive (low speed) signal is given. J ≥ 3 ms Resume (host) Host wants to wake device up. K ≥ 20 ms then EOP pattern Resume (device) Device wants to wake up. (Must be in idle for at least 5 ms.) Device drives K ≥ 1 msHost then sends a resume signal. Keep alive Host wants to tell low speed device to stay awake. EOP pattern once every millisecond. colspan=2
Transmission USB data is transmitted by toggling the data lines between the J state and the opposite K state. USB encodes data using the NRZI line coding:
0 bit is transmitted by toggling the data lines from J to K or vice versa. 1 bit is transmitted by leaving the data lines as-is.
To ensure that there are enough signal transitions for clock recovery to occur in the bitstream, a bit stuffing technique is applied to the data stream: an extra 0 bit is inserted into the data stream after any occurrence of six consecutive 1 bits. (Thus ensuring that there is a 0 bit to cause a transmission state transition.) Seven consecutively received 1 bits are always an error. For USB 3.0, additional data transmission encoding is used to handle the higher signaling rates required.
Transmission example on a full-speed device
Synchronization Pattern A USB packet begins with an 8-bit synchronization sequence, 00000001₂. That is, after the initial idle state J, the data lines toggle KJKJKJKK. The final 1 bit (repeated K state) marks the end of the sync pattern and the beginning of the USB frame. For high-bandwidth USB, the packet begins with a 32-bit synchronization sequence. End of Packet (EOP) EOP is indicated by the transmitter driving 2 bit times of SE0 (D+ and D− both below max.) and 1 bit time of J state. After this, the transmitter ceases to drive the D+/D− lines and the aforementioned pull-up resistors hold it in the J (idle) state. Sometimes skew due to hubs can add as much as one bit time before the SE0 of the end of packet. This extra bit can also result in a bit stuff violation if the six bits before it in the CRC are 1s. This bit should be ignored by receiver. Bus Reset A USB bus is reset using a prolonged (10 to 20 milliseconds) SE0 signal.
High speed negotiation A special protocol during reset, called chirping, is used to negotiate the high speed mode with a host or hub. A device that is high speed capable first connects as a full speed device (D+ pulled high), but upon receiving a USB RESET (both D+ and D− driven LOW by host for 10 to 20 ms) it pulls the D− line high, known as chirp K. This indicates to the host that the device is high bandwidth. If the host/hub is also HS capable, it chirps (returns alternating J and K states on D− and D+ lines) letting the device know that the hub operates at high bandwidth. The device has to receive at least three sets of KJ chirps before it changes to high speed terminations and begins high speed signaling. Because SuperSpeed and beyond uses wiring that is separate and additional to that used by earlier modes, such bandwidth negotiation is not required.
Clock tolerance is 480.00±0.24 Mbit/s, 12.00±0.03 Mbit/s, and 1.50±0.0225 Mbit/s.
USB 3.0